Clamping Modulation Technique for Balancing Power Losses of Dual Inverter With Isolated DC Bus

초록

This paper proposes a clamping modulation technique to reduce and balance power losses in a dual inverter with an isolated DC bus. To drive an open-end winding permanent magnet synchronous motor (OEW-PMSM), dual inverter consisting of six legs has twelve switching actions, twice as many as a two-level voltage source inverter (VSI) per switching period. However, many switching actions cause power losses in switching devices, reducing the efficiency of the system. In this paper, a four-leg clamping modulation technique is presented to reduce the switching actions by analyzing the relationship between two reference voltage vectors of primary and secondary inverters on a space vector plane. To clamp four of the six legs overall, the switching states are determined by combining active and zero vectors during the switching period. The selected vector combinations differ according to 18 sectors divided by the magnitude and angle of the reference voltage vector. The zero vectors required for 18 sectors are then distributed to balance the power losses in upper and lower switching devices of each leg. This technique is implemented with carrier-based pulse width modulation (PWM) by calculating each three-phase reference voltage from two reference voltage vectors composed of the vector combinations. Balancing of the power losses between the upper and lower switching devices is achieved by adding offset voltages corresponding to the zero vector of each sector. The validity of the proposed technique is verified experimentally.

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